Module

This module is concerned with the design and implementation of digital electronic systems that form basic components of modern computers. Topics include an introduction to switching algebra, synthesis of combinational and sequential circuits and techniques for circuit minimization. The module also provides a practical introduction to VHDL, an industry standard hardware description language. Students gain practical experience by undertaking a number of projects based on programmable logic devices.

Teaching Resources:

The module is managed using Blackboard. Copies of lecture slides will be made available on the day of the lecture at the latest. Tutorial sheets will be distributed prior to workshops. Student numbers will be limited to 20 at workshops and laboratories. Laboratory work will be undertaken in the Lewin laboratory.  

Library Resources:

The library contains many text on Digital Electronics. These are mainly to be found at TK. The library holds copies of the course texts (but the latest edition may not necessarily be available.
 

Required purchases:
 

Zwolinski,M., Digital System Design with VHDL, Prentice Hall
 

Possible alternative purchases:
 

Wakerly,J.F., Digital Design: Principles and Practices Prentice Hall

Submission

Written coursework should be submitted by following the standard CMP practice. Students are advised to refer to the Guidelines and Hints on Written Work in CMP.

Deadlines

Coursework should be submitted before 23:59 on the deadline day. Paper copies can be submitted via the Hub drop boxes up to 22.00  in the LTS Hub, and there will be a ‘late box’ in the Library for submissions between 22.00 and midnight.

If coursework is handed in after the deadline day or an agreed extension:
 

 

Work submitted	Marks deducted
On the day following the due date	10 marks
On either the 2nd or 3rd day after the due date	20 marks
On the 4th day after the due date and before the 20th day after the due date	All the marks the work merits if submitted on time (ie no marks awarded)
After 20 working days	Work will not be marked and a mark of zero will be entered

 

All extension requests will be managed through the LTS Hub. A request for an extension to a deadline for the submission of work for assessment should be submitted by the student to the appropriate Learning and Teaching Service Hub, prior to the deadline, on a University Extension Request Form accompanied by appropriate evidence. Extension requests will be considered by the appropriate Learning and Teaching Service Manager in those instances where (a) acceptable extenuating circumstances exist and (b) the request is submitted before the deadline. All other cases will be considered by a Coursework Coordinator in CMP.


Plagiarism

Plagiarism is the copying or close paraphrasing of published or unpublished work, including the work of another student; without due acknowledgement. Plagiarism is regarded a serious offence by the University, and all cases will be investigated. Possible consequences of plagiarism include deduction of marks and disciplinary action, as detailed by UEA’s Policy on Plagiarism and Collusion.

Module Objectives:
Learning Outcomes:

On completion of this module students should be able to:

Subject specific:
 

• Use Boolean Algebra to describe and analyse combinational and sequential circuits.
• Appreciate differences in implementation technologies used in the fabrication of digital electronic circuits and how these affect their electrical characteristics.
• Describe the structure of electronic programmable logic devices.
• Specify the operation of digital electronic circuits using a HDL.
• Synthesise simple combinational and sequential logic circuits to meet specific design criteria.

Transferable skills: Write an appropriately formatted technical report describing work undertaken in the laboratory, including a discussion and critical analysis of the results obtained.

Teaching Approach:

8Concepts will be introduced during lectures and students consolidate their understanding by undertaking tutorial exercises and laboratory work.

Total hours: 50

Lectures: 12, hours: 24, Content (with provisional weekly schedule)

1. Switching algebra; min/max terms; duality; combinational circuit analysis.
2. Minimisation; Karnaugh maps; synthesis of SSI fns. e.g. bcd-7seg. Decoder
3. VHDL coding of primitive gates; comparators, half/full adder.
4. VHDL coding of latches and flip-flops; ripple counters.
5. VHDL coding of synchronous sequential logic circuits; synchronous counters
6. Mealy/Moore state machine models, state machine
7. Introduction to asynchronous state machines.
8. Implementation of state machines in VHDL
9. Electrical characteristics of logic signals and gates;
10. Fabrication techniques for CMOS/TTL logic
11. Electrically programmable logic devices (EPLDs);
12. Revision

Workshops: 10, hours: 10, Content (with provisional weekly schedule)

1. Boolean algebra.
2. Karnaugh maps
3. VHDL Examples 1
4. VHDL Examples 2
5. VHDL Examples 3
6. State machines 1
7. State machines 2
8. Logic conventions, Fan in, Fan out, Noise margin;
9. Logic families.
10. Programmable Devices

Laboratory Work: 8, hours: 16, Content (with provisional weekly schedule)

1. Introduction to Altera Quartus (VHDL + schematic entry)
2. BCD/7-segment decoder (VHDL + schematic entry)
3. Coursework 1
4. Coursework 1
5. Counter 1 (Schematic entry)
6. Counter 2 (VHDL entry)
7. Coursework 2
8. Coursework 2

Method of Assessment:

The module is assessed by a combination of coursework and a formal examination. The examination is of 3 hours duration and accounts for 60% of the marks.

The coursework is divided into two components:

1. Combinational Logic Exercise: Assessed by Bench Presentation
2. Sequential logic Exercise: Assessed by formal report

Both exercises will be implemented using Altera EPLDs (or equivalents).

Setting of coursework:

Coursework will be posted on Blackboard in week 2 and week 4. Blackboard managed tests go live immediately after the lecture and remain available for one week only. Questions must be answered within 1 hour - only one attempt is permitted.